The present invention relates to a data processing system having a buffer memory, and particularly to a system which is suited for a microprocessor which supports a memory mapped I/O system, a multi-processor having a common memory, and the like.
In microcomputers, a memory mapped I/O system has heretofore been widely used to control the input/output device by accessing an input/output control register in the same address space as the main memory using general instructions, without providing special instructions to control the input/output device.
FIG. 1 is a block diagram showing a memory mapped I/O system, wherein a processor 1 controls a main memory 2 and input/output control circuits 3, 5 for respective I/O devices 4, 6 via a system bus 100. Inherent addresses are assigned to the main memory 2, and to the input/output control circuits 3, 5 respectively. Values stored in control registers (not shown) in the input/output control circuits 3, 5 are rewritten by the processor 1, and input/output devices 4, 6 are controlled by the new value in the control registers. Further, when their own statuses are changed, the input/output devices 4, 6 rewrite the values stored in the status registers (not shown) in the input/output control circuits 3, 5. When the contents of the main memory 2 are to be rewritten in response to a store instruction, the processor 1 applies to the system bus 100 a write address assigned to the main memory 2, data to be written and a write command. When the contents of the main memory are to be read out in response to a load instruction, a read address assigned to the main memory 2 and a read command are applied to the system bus 100, and the data sent from the main memory 2 to the system bus 100 is received by the processor 1 as read data. The input/output device 4 starts to operate when a start bit in a control register (not shown) in the input/output control circuit 3 is turned on.
For instance, when the store instruction is to be executed for the control register and an inherent address for the control register is used as the write address of the store instruction, the input/output device 4 starts to operate. On the other hand, to detect the completion of operation of the input/output device 4, the status register (not shown) in the input/output control circuit 3 is read out by the above-mentioned load instruction, and the operation completion bit of the status register is checked to see whether it is on or off. When the operation completion bit is on, other bits of the status register are checked to detect the condition of completion, such as normal completion or abnormal completion.
Using the memory mapped I/O system, as mentioned above, the input/output device can be controlled in a sophisticated manner using general instructions, without the need of providing special input/output instructions,
The microprocessor is often provided with a cache (buffer memory) to improve performance. However, a problem arises, as described below with reference to FIG. 2, if use is made of a system in which a cache is incorporated into the aforementioned memory mapped I/O system. FIG. 2 is a block diagram of a system using a cache (buffer memory) in a memory mapped I/O system.
In FIG. 2, the processor 1 consists of a central processing unit (CPU) 10 for executing instructions, and a cache 11 which stores addresses for referring to the main memory 2 as well as data stored in the regions of the main memory indicated by the addresses. If now it is requested by the CPU 10 to refer to the data in regions of the main memory 2 to effect instruction fetching or data reading, the cache 11 is first checked. When the desired data is found in the cache 11, the data of the cache 11 is sent to the CPU 10 thereby to complete the reading of the data or instruction. However, when the data is not found in the cache 11, the corresponding data is read from the main memory 2 via the system bus 100. The data which is read out is sent to the CPU 10, and at the same time is stored in the cache 11 along with the read addresses thereof. When data is to be written into the main memory 2 from the CPU 10, the write data and the write addresses produced from the CPU 10 are sent to the main memory 2 via the system bus 100, and the corresponding write data is written into the main memory 2. At the same time, the write data and the write addresses are also stored in the cache 11.
The cache 11 has an access speed which is faster than that of the main memory 2. Therefore, since the data in the main memory 2 that is once read out or written also has been stored in the cache 11, the access time for such data can be reduced when reference is made again to the same data by obtaining the data from the cache 11.
However, we recently noticed that a problem will arise as described below when reference is made to the status register (not shown) in the input/output control circuit 3 or 5 in a system of the memory mapped I/O type described when a cache is added to the processor.
It is assumed that the processor 1 executes a program which checks the status register (not shown), and waits for the completion of operation of the input/output device 4. As the CPU 10 makes reference to the status register in the input/output control circuit 3, the value stored in the status register is sent to the CPU 10 and is also stored in the cache 11. The CPU 10 checks the completion bit of the status register. When the completion bit is on, the operation should proceed to the next program instructions. When the completion bit is off, the status register should be read repetitively and the completion bit checked repetitively. When an instruction to read the status register is executed for the second and subsequent times, however, the value stored in the cache 11 is sent back to CPU 10 as the data of the status register. Therefore, even when the input/output operation of the input/output device 4 is completed, and the completion bit of the status register in the input/output control circuit 3 is turned on, the processor 1 is not capable of detecting this fact, because it is looking at old data stored in the cache 11. We further noticed that there also arises a problem that when it is attempted to read out the contents of the status register, the value of the control register is read out instead, in the case when the control register and the status register are allocated to different bits of the same register with the same address, or in the case when the control register and the status register are allocated to the same address, the control register is accessed at the time of writing the data, and the status register is accessed at the time of reading the data. This is because the value written into the control register has been stored in the cache 11 and, when an instruction to read the status register is executed, the data stored in the cache 11 for the control register is read out.
Described below is a problem which we noticed is apt to develop in transferring a message between the buffer memory and the processors in a multiprocessor system in which a plurality of processors are coupled to disperse the load.
A system which performs the processing by transferring messages between two processors is described below with reference to the block diagrams of FIGS. 3 and 4. FIG. 3 is a block diagram of a system which consists of processors 1 and 7, local memories 2 and 2' provided exclusively for these processors, and a main memory 8 for communicating the message between processors via the buses 100 and 101. Usually, each of the processors 1 and 7 performs processing using its own local memory 2 or 2'. When the processor 1 requests the processor 7 to perform processing, however, the processor 1 writes the processing to be done and data necessary for the processing into predetermined regions of the main memory 8, and then interrupts the processor 7. When interrupted, the processor 7 reads the contents of the memory 8, and performs the processing that is requested. When the processing is finished, the processor 7 writes the results into the memory 8 to inform the processor 1, and interrupts the processor 1. Then, the processor 7 resumes the previous processing. Being interrupted by the processor 7, the processor 1 takes out the processed results from the memory 8, and continues processing. When the processing requested to the processor 7 is being executed, the processor 1 carries out other processing using the local memory 2.
FIG. 4 is a block diagram of a system in which the two processors 1 and 7 are connected to a common system bus 100 to commonly use the main memory 2. These processors access the main memory 2 independently from each other. However, when one processor is accessing the main memory 2, the other processor is so controlled that its request for access remains on standby. According to this system, messages between the processors are communicated using a particular region of the main memory 2. Namely, this system is the same as the system shown in FIG. 3, except that the region for writing the message is a particular region in the main memory 2.
In these two systems, if the processors 1 and 7 are provided with general buffer memories 11 and 71, a problem arises as described below. That is, when, for example, the processor 1 writes the data in a region for communicating the message, the value of the cache 11 possessed by the processor 1 is renewed as the data is written. However, the value of the same address is not renewed even when it has been stored in the buffer memory 71 of the processor 7. Accordingly, even when the processor 7 accessses the message region, the data of the buffer memory 71 is read out, and the message of the processor 1 is not correctly received.